1. Field of the Invention
This invention relates to solid state memory cells wherein cross coupled bipolar switching transistors utilize dual collector bipolar transistors as active loads.
2. Related Art
FIG. 1 shows an active load bipolar RAM memory cell 10 referred to as a complementary transistor switch (CTS) cell. Therein bipolar switching transistors 12 and 14 each have their bases connected to the collector of the other switching transistor. Transistors 12 and 14 employ bipolar transistors 16 and 18, respectively, as active loads. Two read/write Schottky diodes 20 and 22, and anti-saturation clamp Schottky diodes 24 and 26 complete cell 10.
In operation, cell 10 is either in standby, read or write mode. In standby, load transistor 16 or 18 is conducting and diodes 20 and 22 are non-conducting. Excess switching transistor base current is directed through anti-saturation diode 24 or 26. This prevents a build-up of carriers in the bases of the switching transistors, thus preparing the cell for fast switching. It also improves the speed of the CTS cell as compared to a standard silicon controlled rectifier (SCR) cell where diodes 24 and 26 are not used.
During a read or write operation, the load transistors are off. Current is supplied to the switching transistors only through the bit lines. For a write, the selected bit line voltage is raised sufficiently to flip the direction of current flow in the switching transistors.
The use of an active load affords a nonlinear voltage response to current injected into the load transistors. Thus, less current is needed to operate the cell than cells employing linear resistors as the load.
A merged transistor layout is employed where the same doped region is used for two different transistors where possible (e.g., the base of transistor 12 is the collector of transistor 16). This, along with the absence of resistors in the cell, results in a very compact structure.
Despite the many advantages of the CTS cell, disadvantages remain. Schottky diodes 20 and 22 must remain on (i.e. be forward biased) in the standby mode. This reduces the voltage differential of the cell thereby reducing noise margins. Further, the dependence on reliable Schottky diodes increases processing difficulties.
A memory cell which retains the advantages of the CTS cell yet affords improved noise margins and does not employ Schottky diodes is highly desirable.